The present invention herein relates to a method of forming a through-hole in a silicon substrate. The present invention herein also relates to a method of forming an electrical connection element which penetrates through the silicon substrate, and to a semiconductor device manufactured thereby. More particularly, the present invention herein relates to a method of forming in a silicon substrate a through-hole capable of reducing roughness in a side wall of the through-hole and exhibiting low permittivity, by alternatingly laminating cationic and anionic polymer on the through-hole that has a dent on the side wall to form a porous elastic layer, and also relates to a method of forming an electrical connection that penetrates through the silicon substrate, and to a semiconductor device manufactured thereby.
The semiconductor integrated circuit manufacturing process is divided into a process for forming devices on a silicon substrate and a process for electrically connecting the devices. Among these processes, the process for electrically connecting the devices is known as an interconnect process or metallization, and as devices become more highly integrated, improving the yield and reliability of the process is critical.
Currently, aluminum is widely used as the metal line material. However, as devices become more highly integrated, the line width decreases while the total length increases, and consequently the signal transfer time delay, which is represented by the resistor-capacitor (RC) time constant, becomes longer. Moreover, as the line width decreases, short circuiting due to electromigration or stress migration becomes a critical limitation. Thus, in order to manufacture fast and reliable devices, there has been much research into using copper, which has a smaller resistivity than aluminum and is strongly resistant to electromigration and stress migration, in ultra large scale integrated circuit devices and as next-generation line material in large-area thin film transistor liquid crystal displays.
However, when copper is used as the line material, there is a disadvantage in that the copper necessitates the use of a diffusion barrier and a junction layer due to limitations of rapid diffusion to a dielectric layer and silicon (Si), and low adhesive strength. As semiconductor device size is reduced to the 22 nm node and below, not only does the thickness of several-nanometer scale diffusion barriers and junction layers become a limitation in pattern filling, expansion of the copper and an adhesion with the lower barrier cause difficulty in later processes.
Regarding this, Korean Patent No. 10-1567888 discloses a semiconductor device method for manufacturing a metal line in a semiconductor device by using an expansion absorbing layer. However, when manufacturing the metal line in the semiconductor device that uses the expansion absorbing layer, the deposition material was regulated in order to achieve a low permittivity, but in such a case there is a disadvantage of being difficult to obtain an ultra low permittivity layer. In order to overcome such a limitation, there is a demand for developing a semiconductor device metal line in which the metal line of the semiconductor device may be manufactured through a simple process, the barrier layer and shock at the copper interconnect may be off set, and an ultra low permittivity property is exhibited.